rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 16-bit dsp dacport ad766 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features zero-chip interface to digital signal processors complete dacport? on-chip voltage reference voltage and current outputs serial, twos-complement input 6 3 v output sample rates to 390 ksps 94 db minimum signal-to-noise ratio C81 db maximum total harmonic distortion 15-bit monotonicity 6 5 v to 6 12 v operation 16-pin plastic and ceramic packages available in commercial, industrial, and military temperature ranges applications digital signal processing noise cancellation radar jamming automatic test equipment precision industrial equipment waveform generation product description the ad766 16-bit dsp dacport provides a direct, three- wire interface to the serial ports of popular dsp processors, in- cluding the adsp-2101, tms320cxx, and dsp56001. no additional glue logic is required. the ad766 is also com- plete, offering on-chip serial-to-parallel input format conver- sion, a 16-bit current-steering dac, voltage reference, and a voltage output op amp. the ad766 is fabricated in analog devices bimos ii mixed-signal process which provides bipolar transistors, mos transistors, and thin-film resistors for preci- sion analog circuits in addition to cmos devices for logic. the design and layout of the ad766 have been optimized for ac performance and are responsible for its guaranteed and tested 94 db signal-to-noise ratio to 20 khz and 79 db snr to 250 khz. laser-trimming the ad766s silicon chromium thin- film resistors reduces total harmonic distortion below C81 db (at 1 khz), a specification also production tested. an optional linearity trim pin allows elimination of midscale differential linearity error for even lower thd with small signals. the ad766s output amplifier provides a 3 v signal with a high slew rate, small glitch, and fast settling. the output ampli- fier is short circuit protected and can withstand indefinite shorts to ground. dacport is a registered trademark of analog devices, inc. the serial interface consists of bit clock, data, and latch enable inputs. the twos-complement data word is clocked msb first on falling clock edges into the serial-to-parallel converter, con- sistent with the serial protocols of popular dsp processors. the input clock can support data transfers up to 12.5 mhz. the falling edge of latch enable updates the internal dac input reg- ister at the sample rate with the sixteen bits most recently clocked into the serial input register. the ad766 operates over a 5 v to 12 v power supply range. the digital supplies, +v l and Cv l , can be separated from the analog signal supplies, +v s and Cv s , for reduced digital crosstalk. separate analog and digital ground pins are also pro- vided. an internal bandgap reference provides a precision volt- age source to the output amp that is stable over temperature and time. power dissipation is typically 120 mw with 5 v supplies and 300 mw with 12 v. the ad766 is available in commercial (0 c to +70 c), industrial (C40 c to +85 c), and military (C55 c to +125 c) grades. commercial and industrial grade parts are available in a 16-pin plastic dip; military parts pro- cessed to mil-std-883b are packaged in a 16-pin ceramic dip. see analog devices military products databook or current military data sheet for specifications for the military version. functional block diagram
rev. a C2C ad766Cspecifications ad766j ad766a parameter min typ max min typ max units resolution 16 16 bits digital inputs v ih 2.0 +v l 2.0 +v l v v il 0.8 0.8 v i ih , v ih = v l 1.0 1.0 m a i il , v il = 0.4 C10 C10 m a serial port timing serial clock period (t clk ) 95 115 ns serial clock hi (t hi )3030ns serial clock lo (t lo )3070ns data valid (t data )4040ns data setup (t s )1520ns data hold (t h )1520ns clock-to-latch-enable (t ctle ) 80 100 ns latch-enable-to-clock (t letc )15 15 ns latch enable hi (t lehi )4040ns latch enable lo (t lelo )40 80ns accuracy 1 gain error 2.0 2.0 % of fsr gain drift 25 25 ppm of fsr/ c midscale output voltage error 30 30 mv bipolar zero drift 4 4 ppm of fsr/ c differential linearity error 0.001 0.001 % of fsr monotonicity 15 15 bits total harmonic distortion f ou t = 1037 hz 1 0 db C88 C81 C88 C81 db C20 db C75 C65 C75 C65 db C60 db C37 C27 C37 C27 db f out = 49.07 khz 2 0 db C77 C72 C77 C72 db C20 db C69 C66 C69 C66 db C60 db C25 C21 C25 C21 db signal-to-noise ratio 3 20 hz to 20 khz (f out = 1037 hz) 1 94 102 94 102 db 20 khz to 250 khz (f out = 49.07 khz) 2 79 83 79 83 db settling time (to 0.0015% of fsr) voltage output 1 6 v step 1.5 1.5 m s 1 lsb step 1.0 1.0 m s slew rate 9 9 v/ m s current output 1 ma step 10 w to 100 w load 350 350 ns 1 k w load 350 350 ns output voltage output configuration 1 bipolar range 2.88 3.0 3.12 2.88 3.0 3.12 v output current 8.0 8.0 ma output impedance 0.1 0.1 w short circuit duration indefinite to common indefinite to common current output configuration bipolar range 0.7 1.0 1.3 0.7 1.0 1.3 ma output impedance ( 30%) 1.7 1.7 k w power supply voltage: +v l and +v s 4.75 13.2 4.75 13.2 v voltage: Cv l and Cv s C13.2 C4.75 C13.2 C4.75 v current case 1 1 : v s and v l = +5 v +i 12.0 15.0 12.0 15.0 ma current case 1 1 : Cv s and Cv l = C5 v Ci C12.0 C15.0 C12.0 C15.0 ma current case 2: 1 v s and v l = +12 v +i 10.5 10.5 ma current case 2: 1 Cv s and Cv l = C12 v Ci C14 C14 ma current case 3 4 : v s and v l = +5 v +i 12 12 ma current case 2: 1 Cv s and Cv l = C12 v Ci C14 C14 ma power dissipation: v s and v l = 5 v 1 120 150 120 150 mw power dissipation: v s and v l = 12 v 300 300 mw power dissipation: v s and v l = +5 v, power dissipation: Cv s and Cv l = C12 v 4 225 225 mw (t min to t max , 6 5 v supplies, f s = 500 ksps unless otherwise noted. no deglitchers or msb trimming is used.)
ad766 rev. a C3C warning! esd sensitive device esd sensitivity the ad766 features input protection circuitry consisting of large distributed diodes and polysilicon series resistors to dissipate both high energy discharges (human body model) and fast, low energy pulses (charged device model). per method 3015.2 of mil-std-883c, the ad766 has been classified as a category 1 device. proper esd precautions are strongly recommended to avoid functional damage or perfor- mance degradation. charges as high as 4000 volts readily accumulate on the human body and test equipment, and discharge without detection. unused devices must be stored in conduc- tive foam or shunts, and the foam discharged to the destination socket before devices are removed. for further information on esd precaution, refer to analog devices esd prevention manual. absolute maximum ratings* v l to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2 v v s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13.2 v Cv l to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . C13.2 v to 0 v Cv s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . C13.2 v to 0 v digital inputs to dgnd . . . . . . . . . . . . . . . . . . . . C0.3 v to v l agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v short circuit protection . . . . . . . . indefinite short to ground soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c, 10 sec *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin designations pin function description 1Cv s analog negative power supply 2 dgnd digital ground 3v l logic positive power supply 4 nc no connection 5 clk clock input 6 le latch enable input 7 data serial data input 8Cv l logic negative power supply 9v out voltage output 10 r f feedback resistor 11 sj summing junction 12 agnd analog ground 13 i out current output 14 msb adj msb adjustment terminal 15 trim msb trimming potentiometer terminal 16 v s analog positive power supply ordering guide temperature package model range option* ad766jn 0 c to +70 c n-16 ad766an C40 c to +85 c n-16 ad766sd/883b C55 c to +125 c d-16 *n = plastic dip; d = ceramic dip. connection diagram ad766j ad766a parameter min typ max min typ max units temperature range specified 0 +70 C40 +85 c storage C60 +100 C60 +100 c notes 1 for a grade only, voltage outputs are guaranteed only if +v s 3 7 v and Cv s C7 v. 2 specified using external op amp, see figure 3 for more details. 3 tested at full-scale input. 4 for a grade only, power supplies must be symmetric, i.e., v s = |Cv s | and + v l = | Cv l | . each supply must independently meet this equality within 5%. all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. specifications subject to change without notice.
ad766Cdefinition of specifications C4C rev. a total harmonic distortion total harmonic distortion (thd) is defined as the ratio of the square root of the sum of the squares of the values of the har- monics to the value of the fundamental input frequency. it is ex- pressed in percent (%) or decibels (db). thd is a measure of the magnitude and distribution of integral linearity error and differential linearity error. the distribution of these errors may be different, depending on the amplitude of the output signal. therefore, to be most useful, thd should be specified for both large and small signal amplitudes. settling time settling time is the time required for the output to reach and remain within a specified error band about its final value, mea- sured from the digital input transition. it is the primary measure of dynamic performance. bipolar zero error bipolar zero error or midscale error is the deviation of the ac- tual analog output from the ideal output (0 v) when the 2s complement input code representing half scale (all 0s) is loaded in the input register. differential linearity error differential linearity error is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in the digital input. monotonic behavior requires that the differential linearity error not exceed 1 lsb in the negative direction. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. signal-to-noise ratio snr is defined as the ratio of the fundamental to the square root of the sum of the squares for the values of all the nonfun- damental, nonharmonic signals for a specified bandwidth. snr is tested at full-scale input. the ad766 specifies snr for 20 khz and 250 khz bandwidths. functional description serial input data is clocked into the ad766s shift register by the falling edge of clk . data is presumed to be in twos complement format with msb (i.e., the sign bit) clocked in first. the shift register converts the most recently clocked-in 16 bits to a parallel word. the falling edge of the latch enable (le) sig- nal causes the most recent parallel word to be transferred to the internal dac input latch. see figure 2 for detailed serial port timing requirements. the contents of the dac input latch cause the 16-bit dac to generate a corresponding current. this 1 ma current is avail- able directly on the i out pin. to use the internal op amp, connect i out (pin 13) directly to the summing junction pin, sj (pin 11) and connect the feedback resistor pin, r f (pin 10) to v out (pin 9). note that the internal op amp is in the inverting configuration. using the internal 3 k w feedback resistor, this op amp will produce 3 v outputs. one advantage of external pins at each end of the feedback resistor is that it allows the user to implement a single pole active low-pass filter simply by adding a capacitor across these pins (pins 10 and 13). the circuit can best be understood redrawn as shown in figure 1. figure 1. low-pass filter using external capacitor the frequency response from this filter will be v out ( s ) i out = - r f r f c s + 1 where r f is 3 k w ( 20%). figure 2. ad766 serial input timing
C5C rev. a the digital ground pin returns ground current from the digital logic portions of the ad766 circuitry. this pin should be con- nected to the digital common point in the system. as illustrated in figure 5, the analog and digital grounds should be connected together at one point in the system. figure 5. recommended circuit schematic power supplies and decoupling the ad766 has four power supply input pins. v s provide the supply voltages to operate the linear portions of the dac in- cluding the voltage reference, output amplifier and control am- plifier. the v s supplies are designed to operate from 5 v to 12 v. the v l supplies operate the digital portions of the chip, in- cluding the input shift register and the input latching circuitry. the v l supplies are also designed to operate from 5 v to 12 v. to assure freedom from latch-up, Cv l should never go more negative than Cv s . special restrictions on power supplies apply to extended tem- perature range versions of the ad766 that do not apply to the commercial ad766j. first, supplies must be symmetric. that is, +v s = u Cv s u and +v l = u Cv l u . each supply must independently meet this equality within 5%. since we require that Cv s Cv l to guarantee latch-up immunity, this symmetry principle implies that the positive analog supply must be greater than or equal to the positive digital supply, i.e., v s 3 Cv l for extended-temper- ature range parts. in other words, the digital supply range must be inside the analog supply range. second, the internal op amps performance in generating voltage outputs is only guaranteed if +v s 3 7 v (and Cv s C7 v, by the symmetry principle). these constraints do not apply to the ad766j. decoupling capacitors should be used on all power supply pins. furthermore, good engineering practice suggests that these ca- pacitors be placed as close as possible to the package pins as well as the common points. the logic supplies, v l , should be decoupled to digital common; and the analog supplies, v s , should be decoupled to analog common. the use of four separate power supplies will reduce feedthrough from the digital portion of the system to the linear portions of the system, thus contributing to the performance as tested. however, four separate voltage supplies are not necessary for good circuit performance. for example, figure 6 illustrates a for applications requiring broader bandwidths and/or even lower noise than that afforded by the ad766s internal op amp, an external op amp can easily by used in its place. i out (pin 13) drives the negative (inverting) input terminal of the external op amp, and its external voltage output is connected to the feed- back resistor pin, r f (pin 10). to insure that the ad766s un- used internal op amp remains in a closed-loop configuration, v out (pin 9) should be tied to the summing junction pin, sj (pin 11). as an example, figure 3 shows the ad766 using the ad744 op amp as an external current-to-voltage converter. in this invert- ing configuration, the ad744 will provide the same 3 v out- put as the internal op amp would have. other recommended amplifiers include the ad845 and ad846. note that a single pole of low-pass filtering could also be attained with this circuit simply by adding a capacitor in parallel with the feedback resis- tor as just shown in figure 1. figure 3. external op amp connections residual dac differential linearity error around midscale can be externally trimmed out, improving thd beyond the ad766s guaranteed tested specifications. this error is most significant with low-amplitude signals because the ratio of the midscale linearity error to the signal amplitude is greatest in this case, thereby increasing thd. the msb adjust circuitry shown in figure 4 can be used for improving thd with low-level sig- nals. otherwise, the ad766 will operate to its specifications with msb adj (pin 14) and trim (pin 15) unconnected. figure 4. optional msb adjustment circuit analog circuit considerations grounding recommendations the ad766 has two ground pins, designated agnd (analog ground) and dgnd (digital ground). the analog ground pin is the high-quality ground reference point for the device. the analog ground pin should be connected to the analog common point in the system. the output load should also be connected to that same point. analog circuit considerationsCad766
ad766 rev. a C6C system where only a single positive and a single negative supply are available. in this case, the positive logic and positive analog supplies may both be connected to the single positive supply. the negative logic and negative analog supplies may both be connected to the single negative supply. performance would benefit from a measure of isolation between the supplies intro- duced by using simple low-pass filters in the individual power supply leads. figure 6. alternate recommended schematic figure 7. power dissipation vs. clock frequency as with most linear circuits, changes in the power supplies will affect the output of the dac. analog devices recommends that well regulated power supplies with less than 1% ripple be incor- porated into the design of any system using these device. measurement of total harmonic distortion the thd specification of a dsp dac represents the amount of undesirable signal produced during reconstruction of a digital waveform. to account for the variety of operating conditions figure 8. distortion test circuit in signal processing applications, the dac is tested at two output frequencies and at three signal levels over the full oper- ating temperature ranges. a block diagram of the test setup is shown in figure 8. in this test setup, a digital data stream, representing a 0 db, C20 db or C60 db sine wave is sent to the device under test. the frequen- cies used are 1037 hz and 49.07 khz. input data is latched into the ad766 at 500 ksps. the ad766 under test produces an analog output signal using the on-board op amp for 1 khz and an external op amp for 50 khz. the automatic test equipment digitizes the output test wave- form, and then an fft to 250 khz is performed on the results of the test. based on the first 9 harmonics of the fundamental 1037 hz and the first 3 harmonics of the 49.07 khz output waves, the total harmonic distortion of the device is calculated. neither a deglitcher nor an msb trim is used during the thd test. the circuit design, layout and manufacturing techniques em- ployed in the production of the ad766 result in excellent thd performance. figure 9 shows the typical unadjusted thd per- formance of the ad766 for various amplitudes of 1 khz and 50 khz sine waves. as can be seen, the ad766 offers excellent performance even at amplitudes as low as 60 db. figure 10 illustrates the typical thd versus frequency performance from the internal amplifier for a filtered ad766 output. at frequen- cies greater than approximately 30 khz, depending on the low- pass filter used, an improvement in thd of 3C4 db over the performance shown in the figure can be achieved. figure 11 illustrates the consistent thd performance of the ad766 over temperature. figure 9. typical unadjusted thd
C7C rev. a applicationsCad766 figure 10. typical thd vs. frequency figure 11. thd vs. temperature interfacing the ad766 to digital signal processors the ad766 is specifically designed to easily interface to several popular digital signal processors (dsp) without any additional logic. such an interface reduces the possibility of interface prob- lems and improves system reliability by minimizing component count. ad766 to adsp-2101 the adsp-2101 incorporates two complete serial ports which can be directly interfaced to the ad766 as shown in figure 12. the sclk, tfs and dt outputs of the adsp-2101 are con- nected directly to the clk , le and data inputs of the ad766, respectively. sclk is internally generated and can be programmed to operate from 94 hz to 6.25 mhz. data (dt) is valid on the falling edge of sclk. after 16 bits have been trans- mitted, the falling edge of tfs updates the ad766s data latch. using both serial ports of the adsp-2101, two ad766s can be directly interfaced with no additional hardware. ad766 to tms320c25 figure 13 shows the zero-chip interface to the tms320c25. the interface to other tms320c2x processors is similar. note that the c25 should be run in continuous mode. the c25s frame synch signal (fsx) will be asserted at the beginning of each 16-bit word but will actually latch in the previous word. figure 12. ad766 to adsp-2101/adsp-2102/ adsp-2105/ adsp-2111 figure 13. ad766 to tms320c25 the clks, fsx and dx outputs of the tms320c25 are con- nected to the clk , le and data inputs of the ad766, re- spectively. data (dx) is valid on the falling edge of clkx. the maximum serial clock rate of the tms320c25 is 5 mhz. ad766 to dsp56000/56001 figure 14 shows the zero-chip interface to the dsp56000/ 56001. the ssi of the 56000/56001 allows serial clock rates up to fosc/4. sck, sc2 and std can be directly connected to the clk , le and data inputs of the ad766. the cra control register of the 56000 allows sck to be internally generated and software configurable to various divisions of the master clock frequency. the data (std) is valid on the falling edge of sck. figure 14. ad766 to dsp56000/dsp56001
ad766 rev. a C8C outline dimensions dimensions shown in inches and (mm). c1385aC16C3/91 printed in u.s.a. 16-pin plastic dip (n-16) d-16 16-lead side brazed ceramic dip
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